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Logos-2

Logos-2 Family FPGAs use advanced 28nm CMOS process. It supports rich on-chip resources and high-performance interface like SerDes, DDR3, and PCIe, providing high-performance programmable solution for customers. Logos-2 is widely used in Communication, Video Processing, Data analysis, Network security, and Measurements.

Product Features

25K~200K LUTs, flexible CLM, each CLM contains 4 LUT6 and 8 Flip-flop

High speed memory interface

DDR3 up to 1066Mbps

Supports LVDS, TMDS, etc. LVDS up to 1.25Gbps

Soft error detection and correction supported

Resolution12 bit, sampling rate 1MSPS

Advanced 256-bit AES encryption

Product Selection Guide

	Part Number		PG2L25H	PG2L50H	PG2L50M	PG2L100H	PG2L100HX¹	PG2L200H
Logic elements	logic Cell		26,700	53,700	44,700	99,900	99,900	239,700
	LUTs		17,800	35,800	29,800	66,600	66,600	159,800
	Flip-Flops		35,600	71,600	59,600	133,200	133,200	319,600
RAM resources	Distributed RAM (Kbit)		344	594	525	1,244	1,244	2,469
	Block RAM(36Kbit each)		55	85	88	155	155	415
	Total block RAM (Kbit)		1,980	3,060	3,168	5,580	5,580	14,940
Clock resources	GPLL+PPLL+FPLL		3+3+0	5+5+0	2+2+2	6+6+0	6+6+0	10+10+0
IO resources	Max. user IO		150	250	146	300	300	500
	Max. differential IO(pairs)		72	120	71	144	144	240
	DDR3(Mbps)		1,066	1,066	\	1,066	1,066	1,066
	DDR4(Mbps)		\	\	1,866	\	\	\
Hard core resources	APM(25*18)		80	120	120	240	240	740
	ADC hard cores		1	1	\	1	1	1
	PCIe Gen2x4		1	1	\	1	1	1
	AES module blocks		1	1	1	1	1	1
	HSST（6.6Gbps/lane）		4	4	\	8	8	16
	MIPI D-PHY hard cores（2.5Gbps/lane）		\	\	2	\	\	\
Package	Dimensions(mm)	Ball Pitch(mm)	User IO / HSST
MBG256	14 x 14	0.8			146/0
MBG324	15 x 15	0.8		210/0		210/0	210/0
MBG325	15 x 15	0.8	150/4
FBG484²	23 x 23	1		250/4		285/4	285/4
FBB484²	23 x 23	1						285/4
FBG676³	27 x 27	1				300/8	300/8
FBB676³	27 x 27	1						400/8
FFBG1156	35 x 35	1						500/16
Note： 1、PG2L100HX supports 1.25Gbps high-speed LVDS 2、FBG484 and FBB484 pin to pin compatible 3、FBG676 and FBB676 pin to pin compatible

Technical Documentation

DS04001_Logos2 Family FPGAs Device Datasheet_V2.1

PK04004_PG2L25H_MBG325_V1.1

PK04005_PG2L50H_FBG484_V1.1

PK04006_PG2L50H_MBG324_V1.1

PK04007_PG2L200H_FFBG1156_V1.0

PK04008_PG2L200H_FBB676_V1.0

PK04009_PG2L200H_FBB484_V1.0

PK04001_PG2L100H_FBG676_V1.3

PK04002_PG2L100H_MBG324_V1.3

PK04003_PG2L100H_FBG484_V1.2

UG040001_Logos2 Family FPGAs Configurable Logic Module (CLM) User Guide_V1.4

UG040002_Logos2 Family FPGA Dedicated RAM Module (DRM) User Guide_V1.2

UG040003_Logos2 Family FPGA Arithmetic Process Module (APM) User Guide_V1.3

UG040004 Logos2 Family FPGAs Clock Resources (Clock) User Guide_V1.2

UG040005_Logos2 Family FPGA Configuration User Guide_V1.3

UG040006_Logos2 Family FPGA InputOutput Interface (IO) User Guide_V1.2

UG040007_Logos2 Family Product GTPs User Guide_V1.2

UG040008_Logos2 Family FPGAs High-Speed Serial Transceiver (HSSTLP) User Guide_V1.9

UG040009_Logos2 Family FPGAs Analog-to-Digital Converter (ADC) ModuleUser Guide_V1.6

UG040012_Logos2 Family Hardware Design Guide_V1.4

Development Boards and Kits

ALINX AXP100B development board

including HDMI input/output, SPF fiber interface

ALINX AXP110 development board

including PCIe 2.0x4, FMC, 1000M Ethernet

Products Titan Family Logos Family Compa Family Pango Design Suite
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